The present invention relates to integrated circuits and more particularly to a grooved channel Schottky contacted MOSFET and a method for making a grooved channel Schottky contacted MOSFET.
In order to more highly integrate electronic circuits, a great deal of research has been focused on small geometry transistors. A Schottky contacted MOSFET has been proposed to eliminate the scaling issues of conventional CMOS. A Schottky contacted MOSFET uses Schottky junctions to replace the conventional heavily-doped p-n homojunctions within the source and drain regions. Metal silicides are used to form natural Schottky barriers to silicon substrates that confine the carriers, reducing or eliminating the need for dopant impurities in the channel to prevent current flow in the xe2x80x9coffxe2x80x99 condition.
Such Schottky contacted MOSFETs are turned on by large gate-induced electric fields at the top of the source region that result in narrowing of the Schottky barrier width and then enhancing the carrier tunneling into the silicon channel. Schottky contacted MOSFETs have the advantage that there is no punch-through because the source barrier is determined by the Schottky barrier itself. Further, random dopant location issues have been eliminated and the external resistance components in the source and drain regions can be reduced because metal silicides directly contact the silicon channel. Therefore, the fabrication of Schottky contacted MOSFETs is more simple than conventional CMOS structures.
Such Schottky contacted MOSFETs still have some drawbacks that prevent their application in logic VLSI and analog circuits. The most important drawback is that the off-state current, which is more than 10xe2x88x928 A/xcexcm, is too large to be used in conventional circuits. Unfortunately, optimizing the design parameters, such as barrier height and background doping, cannot eliminate this drawback.
Another drawback of the Schottky contacted MOSFETs is that they cannot be scaled to less than 30 nm due to severe short-channel effects. As the gate length of a planar Schottky MOSFET is reduced to less than 0.05 xcexcm, the short-channel effects become quite severe. Referring to FIG. 11, a graph of drain current versus gate voltage of a planar Schottky MOSFET having a gate length of 20 nm is shown. Curves 400, 402 and 404 illustrate the device operating at drain voltages of 0.75 v, 0.35 v and 0.1 v, respectively. As can be seen for this device, the threshold voltage decreases as the drain voltage (Vds) increases. In the meantime, the off-state current increases, which is similar to the punch-through effect in conventional CMOS devices. These characteristics prevent conventional Schottky contacted MOSFETs from use in commercial applications, such as logic VLSI and analog integrated circuits.
It is an object of the present invention to provide a Schottky contacted MOSFET suitable for VLSI and analog circuit applications.
In order to provide a Schottky contacted MOSFET that is suitable for VLSI and analog circuit applications, the present invention provides a grooved channel Schottky contacted MOSFET with a metal gate and asymmetric Schottky contacted source and drain regions.
In a first embodiment, the invention provides a semiconductor device including a silicon substrate having a grooved channel formed in a first surface thereof. A first metal silicide material is formed on the first surface on a first side of the grooved channel, which defines a source region. A second metal silicide material is formed on the first surface on a second side of the grooved channel, which defines a drain region. A metal gate is formed in the grooved channel.
In accordance with the invention, a N-channel grooved Schottky MOSFET includes an undoped silicon or P-doped silicon substrate having a background doping concentration of less than about 1017 cmxe2x88x923. A grooved channel is formed in a first surface of the substrate. A PtSi layer is formed on the first surface on a first side of the grooved channel, which defines a source region. An ErSi layer is formed on the first surface on a second side of the grooved channel, which defines a drain region. A gate made of TiSi2 is formed in the grooved channel. The gate has a length of about 0.03 um or less. An off-state current of the MOSFET is less than about 50 pA/um and an on-state current is greater than about 200 uA/um.
The invention further provides a P-channel grooved Schottky MOSFET including an undoped silicon or N-doped silicon substrate having a background doping concentration of less than about 1017 cmxe2x88x923. A grooved channel is formed in a first surface of the substrate. An ErSi layer is formed on the first surface on a first side of the grooved channel, which defines a source region and a PtSi layer is formed on the first surface on a second side of the grooved channel, which defines a drain region. A metal gate is formed in the grooved channel. The gate is made of a metal having a work function of about 5.0 eV and a gate length of less than about 0.03 um. An off-state current of the MOSFET is less than about 50 pA/um and an on-state current is greater than about 200 uA/um.
The present invention also provides a method of fabricating a grooved channel Schottky contacted MOSFET including the steps of:
providing an undoped silicon substrate having a background doping concentration of less than 1017 cmxe2x88x923;
forming an isolation trench in a first surface of the substrate;
depositing a thin oxide film on the first surface of the substrate;
depositing a thin nitride film over the thin oxide film;
forming first and second grooved channels in the first surface of the substrate wherein the first and second grooved channels are formed on opposing sides of the isolation trench;
forming a first metal gate in the first grooved channel and a second metal gate in the second grooved channel;
depositing a first metal on the first surface of the substrate on first sides of the first and second channels, the first sides being located between the isolation trench and the first and second channels, respectively, and annealing the first metal to form a first metal silicide, thereby defining a drain of a p-channel device and a source of a n-channel device; and
depositing a second metal on the first surface of the substrate on second sides of the first and second channels, the second sides opposing the first sides, and annealing the second metal to form a second metal silicide, thereby defining a source of the p-channel device and a drain of the n-channel device.